The invention relates generally to forming protective layers prior to alternating layer deposition (ALD). More particularly, the invention relates to forming sealing layers prior to high conformality ALD layers over porous layers in integrated circuits.
When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned to produce desired structures. xe2x80x9cBack endxe2x80x9d or metallization processes include contact formation and metal line or wire formation. Contact formation vertically connects conductive layers through an insulating layer. Conventionally, contact vias or openings are formed in the insulating layer, which typically comprises a form of oxide such as borophosphosilicate glass (BPSG) or an oxide formed from tetraethylorthosilicate (TEOS) precursors. The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring above and below the insulating layers. The layers interconnected by vertical contacts typically include horizontal metal lines running across the integrated circuit. Such lines are conventionally formed by depositing a metal layer over the insulating layer, masking the metal layer in a desired wiring pattern, and etching away metal between the desired wires or conductive lines.
Damascene processing involves forming trenches in the pattern of the desired lines, filling or overfilling the trenches with a metal or other conductive material, and then etching the excess metal back to the insulating layer. Wires are thus left within the trenches, isolated from one another in the desired pattern. The etch back process avoids the more difficult photolithographic mask and etching processes of conventional metal line definition.
In an extension of damascene processing, a process known as dual damascene involves forming two insulating layers, typically separated by an etch stop material, and forming trenches in the upper insulating layer, as described above for damascene processing. After the trenches have been etched, a further mask is employed to etch contact vias downwardly through the floor of the trenches and the lower insulating layer to expose lower conductive elements where contacts are desired.
Conductive elements, such as gate electrodes, capacitors, contacts, runners and wiring layers, must each be electrically isolated from one another for proper integrated circuit operation. In addition to providing insulating layers around such conductive elements, care must be taken to prevent diffusion and spiking of conductive materials through the insulating layers, which can cause undesired short circuits among devices and lines. Protective barriers are often formed between via or trench walls and metals in a substrate assembly to aid in confining deposited material within the via or trench walls. Barriers are thus useful for damascene and dual damascene interconnect applications, particularly for small, fast-diffusing elements such as copper.
Candidate materials for protective barriers should foremost exhibit effective diffusion barrier properties. Additionally, the materials should demonstrate good adhesion with adjacent materials (e.g., oxide via walls, adhesion layers, etch stop layers and/or metallic materials that fill the vias and trenches). For many applications, a barrier layer is positioned in a current flow path and so must be conductive. Typically, barriers have been formed of metal nitrides (MNx), such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), which are dense and adequately conductive for lining contact vias, wiring trenches, and other conductive barrier applications.
These lined vias or trenches are then filled with metal by any of a variety of processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and electroplating. For effective conductivity and to avoid electromigration during operation, the metal of a contact or wiring layer should fill the via or trench without leaving voids or key holes. Completely filling deep, narrow openings with conductive material is becoming ever more challenging as integrated circuit dimensions are constantly scaled down in pursuit of faster operational processing speeds and lower power consumption.
As illustrated in FIGS. 1 and 2, utilizing a conductive barrier layer and/or other liners makes filling the trenches and vias of dual damascene processing even more difficult. FIG. 1 illustrates a dual damascene process in which an upper insulating layer 10 is formed over a lower insulating layer 12, which is in turn formed over a conductive wiring layer 14, preferably with an intervening dielectric diffusion barrier 15. This dielectric barrier 15 serves to prevent copper or other conductive material of the underlying runner 14 from diffusing into the overlying dielectric layer 12.
A mask is employed to pattern and etch trenches 16 in a desired wiring pattern. In the illustrated embodiment, the trench 16 is etched down to the level of an etch stop layer 19, which is formed between the two insulating layers 10, 12. This etch stop layer 19 is typically patterned and etched, prior to deposition of the upper insulating layer 10, to form a hard mask that defines horizontal dimensions of desired contact vias that are to extend from the bottom of the trench 16. Continued etching through the hard mask 19 opens a contact via 20 from the bottom of the trench 16 to the lower conductive wiring layer 14. FIG. 1 also shows an upper etch stop or chemical mechanical polishing (CMP) stop layer 21 over the upper insulating layer 10 to stop a later planarization step, as will be appreciated by the skilled artisan.
Protective liners 22, preferably formed of conductive material, are then formed on the exposed horizontal and sidewall surfaces. Typically, the liners 22 at least include a metal nitride, and may additionally include adhesion enhancing and seeding layers. For example, the liner 22 can comprise a tri-layer of Ti/TiN/Cu. In such a structure, the titanium layer serves to improve adhesion with exposed oxide sidewalls; the titanium nitride serves as a diffusion barrier; and a thin copper layer serves as a seed for later electroplating of copper. In other examples, the liners 22 can include tantalum nitride or tungsten nitride barriers. The skilled artisan will appreciate that other barrier materials can also be employed.
Conformal deposition of the liners 22, however, is very difficult with conventional processing. For example, physical vapor deposition (PVD), such as sputtering, of a metal layer (for adhesion, barrier and/or seed layer) requires at least about 50 xc3x85 over all surfaces of the trench 16 and contact via 20. Unfortunately, PVD of metal into high aspect ratio voids necessitates much greater deposition on the top surfaces of the workpiece to produce adequate coverage of the via bottom. For example, typical state-of-the-art trench and contact structures for dual damascene schemes require about 500 xc3x85 PVD metal in order for 50 xc3x85 of metal to reach the bottom and sidewalls of the contact via 20.
This poor step coverage is a result of the high aspect ratio of voids formed for dual damascene processing in today""s integrated circuit designs. The aspect ratio of a contact via is defined as the ratio of depth or height to width. In the case of dual damascene contacts, the trench 16 and contact via 20 together reach through two levels of insulating layers 10, 12, such that the effective aspect ratio of the via 20 is very high.
Conventional deposition processes produce very poor step coverage (i.e., the ratio of sidewall coverage to field or horizontal surface coverage) of such high aspect ratio vias for a variety of reasons. Due to the directionality of PVD techniques, for example, deposition tends to accumulate more rapidly at upper corners 26 of the trench 16 and upper corners 28 of the via 20, as compared to the via bottom 30. As a result of the rapid build-up of deposited material on the upper surfaces of the structure, the liners occupy much of the conductive line width in the trench 16 and even more, proportionately, of the contact via 20. These built-up corners 26, 28 then cast a shadow into the lower reaches of the structure, such that lower surfaces, and particularly lower corners, are sheltered from further deposition. Although PVD deposition can be directed more specifically to the via bottom, e.g., by collimation or by ionization of the depositing vapor, such additional directionality tends to sacrifice sidewall coverage.
Chemical vapor deposition (CVD) processes have been developed for certain metals and metal nitrides. CVD tends to exhibit better step coverage than PVD processes. In order for CVD processes to exhibit good step coverage, the reaction must be operated in the so-called xe2x80x9csurface controlledxe2x80x9d regime. In this regime, reaction species do not adhere to trench or via walls upon initial impingement. Rather, the species bounce off trench/via surfaces several times (e.g., 10-500 times) before reacting.
State-of-the-art CVD processes for depositing barrier layers at temperatures sufficiently low to be compatible with surrounding materials do not operate completely within the surface-controlled regime. Accordingly, even CVD processes tend to deposit far less material at the bottom of a dual damascene contact via 20 then on the upper surfaces and sidewalls of the structure. The upper corners of the trench 16 and the contact via 20 represent a high concentration of surface area to volume. Deposition upon the horizontal upper surfaces and adjacent vertical sidewall surfaces merge together to result in an increased deposition rate near the corners 26, 28. Additionally, flowing reactants diffuse slowly into the confined spaces of the trench 16 and contact via 20. Accordingly, the concentration of reactants reaching the via bottom 30 is far reduced relative to the concentration of reactants reaching upper surfaces of the structure. Thus, while somewhat improved relative to PVD, CVD step coverage of dual damascene structures remains uneven with most currently known low temperature CVD techniques.
In the pursuit of faster operational speeds and lower power consumption, dimensions within integrated circuits are constantly being scaled down. With continued scaling, the aspect ratio of contacts and trenches continues to increase. This is due to the fact that, while the width or horizontal dimensions of structures in integrated circuits continues to shrink, the thickness of insulating layers separating metal layers cannot be commensurately reduced. Reduction of the thickness in the insulating layers is limited by the phenomenon of parasitic capacitance, whereby charged carriers are slowed down or tied up by capacitance across dielectric layers sandwiched by conductive wires. As is known, such parasitic capacitance would become disabling if the insulating layer were made proportionately thinner as horizontal dimensions are scaled down.
With reference to FIG. 2, a scaled-down version of FIG. 1 is depicted, wherein like parts are referenced by like numerals with the addition of the suffix xe2x80x9ca.xe2x80x9d As shown, continued scaling leads to a more pronounced effect of uneven step coverage while lining dual damascene structures. Material build-up at the corners 28a of the contact via 20a quickly reduces the size of the opening, even further reducing the concentration of reactants that reach into the contact via 20a. Accordingly, coverage of the via bottom surface 30a drops off even faster. Moreover, the percentage of the trench 16a occupied by the liner materials is much greater for the scaled down structure of FIG. 2. Since the lining material is typically less conductive than the subsequent filler metal (e.g., copper), overall conductivity is reduced. Worse yet, cusps at the corners 28a of the contact via can pinch off before the bottom 30a is sufficiently covered, or during deposition of the filler metal.
Independently of efforts to improve barrier film uniformity are efforts to reduce the dielectric or permittivity constant (k) value of the interlevel dielectric (ILD) material. A reduced dielectric constant value results in less parasitic capacitance per unit thickness of the ILD, such that for a given circuit design tolerance for parasitic capacitance, a so-called xe2x80x9clow kxe2x80x9d material can provide a thinner ILD. xe2x80x9cLow kxe2x80x9d designates a material with a k value below that of silicon oxide (k≈4), the currently predominant ILD material in integrated circuit fabrication. Accordingly, the aspect ratio of contacts and trenches to be filled can be reduced and lining these openings becomes easier.
A variety of materials and techniques are being developed for producing low k films in integrated circuits. Deposition methods currently include spin-on deposition, CVD, plasma enhanced CVD (PECVD) and high density plasma (HDP) CVD, depending upon the characteristics desired. Some of the methods and films have been described by Laura Peters, xe2x80x9cPursuing the Perfect Low-k Dielectricxe2x80x9d Semiconductor International, Vol. 21, No. 10 (September 1998), and the references cited therein. Some films have a k value from 3 to 3.5 such as hydrogen silsesquioxane (HSQ) and fluorinated oxides. Organic polymers, such as benzoncyclobutene (BCB) and polyarylene ethers (PAE), exhibit even lower k values between 2.5 and 3 range. Other work with polytetrafluoroethylene (PTFE) using spin-on techniques has achieved intrisic k values of about 1.9. Other companies have created nanoporous inorganic-organic hybrids.
Use of such low k materials as an ILD in an integrated circuit will considerably reduce the aspect ratios of openings in the ILD. Accordingly, lining such openings with adequate conformality should prove simpler as compared with lining openings with higher aspect ratios.
Integrating these new materials with existing technologies, however, introduces its own challenges. Among other requirements, low k films must exhibit high chemical, thermal and mechanical stability in the face of disparate adjacent materials and exposure to a variety of processing environments. ILD materials should be compatible with etching, deposition, cleaning and polishing processes in order to integrate reliably with a manufacturing process. As will be appreciated by the skilled artisan, integration of new materials and processes into established process flows is rarely a straightforward matter, as evidenced by complications arising from the introduction of copper lines into state-of-the-art integrated circuit designs.
It would accordingly be advantageous to provide low k material without changing the material characteristics of the ILD with each succeeding generation. One manner in which the k value of a material can be lowered without changing the material properties of the ILD is to make the material porous. In effect, porous dielectrics combine the dielectric strength of air (k≈1.0) with that of the dielectric material in which the pores are formed. Advantageously, the k value of a porous material is xe2x80x9ctunablexe2x80x9d in the sense that the k value can be altered without introducing new materials by changing the porosity of a material that has already been integrated.
Currently silicon oxide (k≈4) is widely used in process flows. Porous versions of silicon oxide or xe2x80x9csilicaxe2x80x9d can have both a low k value and compatibility with current process flows. This has led to the development of classes of porous silica known as nanogels, aerogels, xerogels and mesogels. Similarly, newer low k materials, once integrated into process flows, can have their k values tuned by adjusting porosity of the low k material. With low k materials currently under development, it appears that achieving k values below 2.5 will likely involve providing a porous insulating material.
While low k films, and particularly porous low k films, can effectively lower the aspect ratio of openings in an ILD, room remains for improvements in lining technology. Although CVD and PVD may adequately line a low aspect ratio opening, non-conformality of conventional deposition techniques can still be problematic.
Accordingly, a need exists for more effective methods of lining openings in integrated circuits, particularly in the context of dual damascene metallization.
In satisfaction of this need, methods are provided herein for depositing lining materials into the high-aspect ratio trenches and contact vias of dual damascene metallization schemes. Advantageously, the methods attain high step coverage, such that only the minimum required thickness of the lining layer need be formed on all surfaces. Examples are provided for applying the methods to formation of one or more of adhesion, barrier and electroplating seed layers.
In general, the methods comprise cycles of alternating reactant phases, wherein each phase has a self-limiting effect. xe2x80x9cPurexe2x80x9d metal layers, for example, can be formed by alternately adsorbing self-saturating halide- or organic-terminated metal monolayers and reducing the metal-containing monolayer. Metal nitrides suitable for conductive diffusion barriers can be formed by alternately adsorbing self-terminated metal-containing monolayers and conducting ligand exchange reactions, substituting nitrogen-containing species for halogen or organic tails on the metal-containing monolayers. Alternatively, the tails of the self-terminated metal-containing monolayer can be reduced or otherwise removed in an intermediate scavenger or getter phase prior to the nitrogen phase.
More particularly, the methods are applied to metallization structures formed in porous xe2x80x9clow kxe2x80x9d materials. Prior to the highly conformal self-saturating processes noted above, a sealing layer is first formed over exposed porous surfaces, blocking the pores. The conformal self-saturating processes cannot then penetrate the pores and the low k dielectric maintains its desired properties. Advantageously, the sealing layer can be metal and subsequent uniformly thick conductive layers can be formed within high-aspect ratio openings (e.g., trenches and vias), desirably as thin as possible consistent with their respective functions, and without risking short circuits through the porous insulating layer. The remaining volume within such openings is thus maximized, facilitating a greater proportionate volume of more highly conductive filler materials, such as copper for metal runners and integral contacts.
For some structures with openings, pores have been found to be particularly problematic for upper surfaces of the structures, such as low k layers that have been found to have primarily vertically aligned pores. Accordingly, it may be desirable to seal or block such upper surface pores without the same concerns for pores on sidewall surfaces deep within openings like trenches.
In one embodiment, such surfaces can be sealed or blocked without depositing a layer. Rather, the upper surface can be morphed or reformed to a selected depth, such that the pores close to the upper surfaces collapse. For example, targeted energy (e.g., pulsed laser or radiant heat) can be provided such that the upper surface to a selected depth is melted. Where the surfaces are found in an interlevel dielectric (ILD) of an integrated circuit, the depth is desirably selected to be close to the minimum depth necessary to ensure that subsequent depositions do not risk short circuiting current across the ILD
In another embodiment, a sealing layer is formed. Similar to sealing damascene structures in conventional low k porous materials, the sealing layer is desirably less conformal than that of conventional atomic layer deposition (ALD). Traditionally, ALD affords near perfect conformality from upper surfaces, along sidewall surfaces, and along bottom surfaces. In this embodiment, it is desirable to afford reduced conformality, such that reduced film thickness results along inner surfaces of openings in the substrate. Thus, conventional CVD and PVD processes can be employed for such a sealing layer.
In a particularly preferred arrangement, however, methods described herein allow tailored conformality, ranging from near perfect conformality of ALD to the level of conformality afforded by chemical vapor deposition (CVD). The inventors have discovered that such tailoring can be useful for a variety of situations in which differential conformality is desired for different structures. For example, the low k layers that have been found to have primarily vertically aligned pores may call for a different level of conformality as compared to the conventional porous low k materials. Whereas coverage of sidewall trench/via surfaces is desired for conventional, isotropically porous layers, such sidewall coverage is not necessary when only horizontal surfaces open into continuous pores. In fact, it may be advantageous to avoid full coverage of the sidewalls for a variety of reasons, such as for leaving maximum room in trenches and vias for highly conductive material (e.g., copper), or for avoiding a directional etch to open up a conductivity path on the bottom of the trenches or vias when an insulating sealing layer is selected.
Accordingly, in accordance with another aspect of the present invention, a method is provided for fabricating an integrated circuit that includes a porous insulating layer having a plurality of trenches extending from an upper surface of the insulating layer. The method includes blocking the pores on an exposed surface of the insulating layer. Blocking is performed preferentially upon upper surfaces of the insulating layer. After blocking the pores, no more than about one monolayer of a first reactant species is formed in a self-limited and self-saturating reaction. A second reactant species then reacts with the monolayer. In one embodiment, blocking is conducted by melting upper surfaces of the substrate. In another embodiment, blocking is conducted by a nonconformal deposition.
In accordance with another aspect of the invention, a method is provided for depositing a film over a structure having openings therein. The method includes an alternating deposition process, whereby a plurality of sequential reactant pulses are separated from one another. This alternating process is optimized to achieve a level of conformality between that of atomic layer deposition (ALD) and chemical vapor deposition.
In accordance with another aspect of the invention, a method is provided for controlling conformality of a deposited film on a semiconductor substrate. The method includes providing the substrate with a plurality of openings at a surface thereof. A sequence is provided of at least two different, mutually reactive reactants in temporally separated and alternating reactant pulses. Separations of the reactant pulses and durations of the reactant pulses are selected to control the conformality of the film deposited in the openings in the surface of the semiconductor substrate, wherein the separations and durations are selected to achieve reduced conformality compared to a corresponding atomic layer deposition (ALD) process that is optimized to achieve maximum conformality with minimum cycle length for the substrate topography. The semiconductor substrate is exposed to the sequence of the reactant pulses with the selected separations and durations to deposit the film.
In accordance with another aspect of the invention, a semiconductor fabrication process includes providing a low k dielectric having an anisotropic pore structure and larger openings therein. An upper surface of the low k dielectric layer is preferentially sealed. An atomic layer deposition process is then conducted to deposit directly over the sealed upper surface.
In accordance with another aspect of the invention, a method for deposition of a film on a semiconductor substrate includes providing the substrate with a surface having different regions with different levels of accessibility. A sequence of at least two different, mutually reactive reactants is provided with temporally separated and alternating reactant pulses. Separation of the reactant pulses and/or duration of the reactant pulses are selected to achieve self-saturation and self-limiting atomic layer deposition (ALD) mode deposition on the most accessible regions on the substrate surface and depletion effects in less accessible regions on the substrate surface. The semiconductor substrate is exposed to the sequence of the reactant pulses with the selected temporal separation and duration to deposit the film.